When a number of independent power modules are sharing a bus line, there is a need to achieve current balance between the power modules during steady state, system power up, system power down and load transients. FIGS. 1-3 illustrate prior art implementations for achieving a current balance between multiple independent power modules during these conditions.
FIG. 1 illustrates a configuration wherein a correction current 102 (ICOR) is a current sink to the negative input of an error amplifier 104. The output of the error amplifier 104 is connected to the COMP pin of the associated power module. The positive input of the error amplifier 104 is connected to receive a reference voltage VREF. The negative input of the error amplifier 104 is also connected to the FB pin of the associated power module. A resistor 106 is connected between the FB pin and the output of a buffered differential amplifier 108. The inputs of the buffered differential amplifier 108 are connected to a resistor divider network consisting of a resistor RFB and a resistor ROS. The resister RFB 110 is connected between the output voltage VOUT and node 114 connected to the positive input of the buffered differential amplifier 108. The resister ROS 112 is connected between node 114 and ground node 116. Ground node 116 is also connected to the negative input of the differential amplifier 108. While the configuration of FIG. 1 provides for current sharing, it limits the choices for the feedback resistor 106 and for choices of the resistors of the compensation network consisting of resistors RFB and ROS 110 and 112.
FIG. 2 illustrates an alternative configuration wherein the error amplifier 204 has its output connected to the COMP pin of the associated power module. The negative input of the error amplifier 204 connected to the FB pin 218 of the associated power module and the positive input is connected to receive a reference voltage VREF. The feedback resistor 206 is connected between the FB pin and the output of a buffered differential amplifier 208. In the configuration of FIG. 2, the correction current ICOR 202 is sourced to the positive input of buffered differential amplifier 208. The resistor divider network consisting of RFB resistor 210 and ROS resistor 212 are connected to the inputs of the buffered differential amplifier. Resistor RFB 210 is connected between the output voltage VOUT and node 214. The ROS resistor 212 is connected between node 214 and ground node 216. The negative input of the buffered differential amplifier 208 is also connected to the ground node 216. The configuration of FIG. 2 limits the choices of the resistor divider consisting of RFB resistor 210 and ROS resistor 212 and is not suitable for a wide range of output voltage applications which may require different combinations of the voltage divider network consisting of resistors 210 and 212.
FIG. 3 illustrates yet another further prior art configuration having a setup similar to that of FIGS. 1 and 2. An error amplifier 304 has its output connected to the COMP pin of the independent power module and its negative input connected to the FB pin of the independent power module. The positive input of the error amplifier has a voltage VREF applied to it through a resistor 318. The correction current, ICOR, is sourced to the positive input of the error amplifier 304. Resistor 306 is connected to the FB pin and to the output of a buffered differential amplifier 308. The positive and negative inputs of the buffered differential amplifier 308 are connected to a resistor divider network consisting of resistor RFB 310 and the resistor ROS 312. The RFB resistor 310 is connected between a voltage VOUT and node 314. The ROS resistor 312 is connected between node 314 and ground node 316, which is also connected to the negative input of the buffered differential amplifier 308. The configuration of FIG. 3 limits the current sharing range without an accessible VREF node. The configuration also affects overall output voltage accuracy when current sharing is not needed.
Thus, what is needed is a new configuration that may be used when limited pins are available on an independent power module in order to overcome the above-described limitations of FIGS. 1 though 3 without introducing an extra pin upon the independent power module package. It would additionally be desirable that this current sharing loop of the IC (controller) can be disabled and make no output voltage correction, but can be used to adjust the internal COMP voltage of the IC in multi-phase operation required multiple ICs.